SK hynix developing split-cell 5-bit flash

SK hynix presented its latest 5-bit cell NAND flash technology at the San Francisco 2025 IEDM conference in December. The approach splits 3D NAND cells in half, increasing the bit level while reducing the number of voltage states required by around two-thirds, which the company says improves speed and endurance.

SK hynix presented topic 18-5: Multi-Site Cells for Penta-Level Cell NAND. It has been working on this so-called 4D 2.0 technology at least since 2022. The idea is to sidestep a voltage state barrier, preventing simply adding bit levels to a NAND cell beyond 4 (QLC).

A NAND cell stores charge, which is read by measuring the threshold voltage at which the cell begins to conduct current. If it passes or does not pass current, that signals binary states: pass/no-pass, on or off, one or zero. You need only two voltage states in a 1-bit or single-level cell (SLC), but the state number doubles as an extra bit is added to the cell:

• 1-bit, SLC = 0 or 1 – meaning two states and one threshold voltage
• 2-bit, MLC = 00, 10, 01, or 11 – four states and so three threshold voltages
• 3-bit, TLC = 000, 001, 010, 011, 100, 101, 110, 111 – eight states and thus seven threshold voltages,
• 4-bit, QLC = 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 – 16 states and so 15 threshold voltages
• 5-bit, PLC = 00000, 00001, 00010, 00011, 00100, 00101, 00110, 00111, 01000, 01001, 01010, 01011, 01100, 01101, 01110, 01111, 10000, 10001, 10010, 10011, 10100, 10101, 10110, 10111, 11000, 11001, 11010, 11011, 11100, 11101, 11110, 11111 – 32 states and so 31 threshold voltages

Adding voltage states narrows the gap between each state and decreases the sensing margin. As each bit is added, it takes longer to program and read the cell’s contents, while the stored electrons leak over time, weakening the voltage state and making the bit level progressively harder to sense until it becomes unreliable. The cells wear out faster when additional bits are added as well.

Currently QLC 3D NAND flash is being fabricated commercially but not PLC, as a PLC cell’s reading reliability is too low and so is its endurance. But PLC is an attractive idea as it adds 25 percent more capacity to a NAND die, and hence SSDs, compared to QLC technology. We could add more capacity to an SSD by increasing the number of layers in the 3D NAND stacks inside each NAND die, but this involves more and difficult semiconductor process steps.

If PLC technology could increase cell capacity with fewer and less difficult process steps than additional layering, without the speed and endurance disadvantages of current technology, then it would be attractive to NAND manufacturers. SK Hynix thinks it could have a way to do this by effectively splitting a NAND cell into two halves or sites, each with fewer and independent voltage states, and building bit values by combining the two sites’ values.

Here is a diagram comparing existing multi-level cell (MLC) technology, seen from above the cell, with the multi-site cell (MSC) concept:

There are extra semiconductor process steps to do this, such as dividing the elliptical cell in two, filling in the gap so as to create a wall, and adding the bit line connections to each half.

There are six voltage states in each site (half-cell) and multiplying them together gets 36 overall voltage states. These can give us the 32 states needed for PLC flash, with four states being ignored, as a table shows:

With both half-cells erased (ERS state), the bit value is 11111.

Because each site only has six voltage states, the gaps between them can be larger, rendering electron leakage less of a problem, and shortening the program time. This also lengthens the cell’s endurance. The two halves of an MSC cell are read simultaneously, in tandem.

The company says the read speed increases 20x compared to non-MSC PLC flash.

SK Hynix effectively presented a semiconductor engineering research paper at the 2025 IEDM conference. It has built wafers with working devices and will be looking at how it could manufacture PLC MSC flash cost-effectively. So too will the other flash fabricators: Kioxia, Micron, Samsung, and Sandisk.

Comment

If you give an MSC half-cell eight voltage states, the result for the whole cell would be 64 voltage states (8 x 8 = 64), enough for a 6-bit hexa-level cell (HLC). This could have the speed of an existing TLC cell, endurance similar to a TLC cell, and provide 50 percent more capacity than a QLC die. An SK Hynix insight article discusses the MSC concept, and an SK Hynix video has a basic look at MSC technology with some diagrams: